虞志益

教授

中山大学电子与信息工程学院,教授、博士生导师

美国卡内基梅隆大学(CMU)电子与计算机工程系,兼职教授

联系方式:yuzhiyi@mail.sysu.edu.cn

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现招聘特聘研究员、特聘副研究员。方向包括:集成电路器件、集成电路设计、计算机体系结构。长期有效,欢迎加盟。

也欢迎博士研究生、硕士研究生加入到我们的团队。

学术兼职和社会服务: 

IEEE Senior Member    

中国异构架构标准工作组,片上互连工作组主席                                                                  

亚太信号与信息处理协会(APSIPA) Signal Processing Systems技术委员会,副主席        

《半导体学报》编委会委员                                                                

ASSCC、ASICON等一系列国际学术会议的技术委员会成员

教育经历: 

美国加州大学Davis分校,电子与计算机工程系,博士                                            

复旦大学微电子系,硕士                                                                  

复旦大学电子工程系,本科                                                                                              

授课课程: 

数字集成电路设计

微机原理

研究方向: 

集成电路设计、处理器设计、基于非易失器件的电路与系统、面向人工智能深度学习等应用的电路与系统

科研项目: 

国家重点研发计划纳米专项、国家自然科学基金面上项目等

代表性科研成果: 
  1. Sai Manoj P.D, Jie Lin, Shikai Zhu, Yingying Yin, Xu Liu, Xiwei Huang, Chongshen Song, Wenqi Zhang, Mei Yan, Zhiyi Yu, Hao Yu, “A Scalable Network-on-Chip Microprocessor with 2.5D Integrated Memory and Accelerator”, IEEE Transactions on Circuits and Systems I, Vol. 64, Issue 6, pp. 1432-1443, 2017.
  2. Weijing shi, Xin Li, Zhiyi Yu, Gary Overett, “An FPGA-Based Hardware Accelerator for Traffic Sign Detection”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, Issue 4, pp. 1362-1372, 2017.
  3. Jianming Yu, Wei Zhou, Yueming Yang, Xiaodong Zhang, Zhiyi Yu, “Manycore Processors Granularity Evaluation Considering Performance, Yield and Lifetime Reliability”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, No. 10, pp. 2043-2053, Oct 2015.
  4. Jie Lin, Shikai Zhu, Zhiyi Yu, Dongjun Xu, Sai Manoj P.D, Hao Yu, “A Scalable and Reconfigurable 2.5D Integrated Multicore Processor on Silicon Interposer”, in IEEE Custom Integrated Circuits Conference (CICC), September 2015.
  5. Xiaoyang Zeng, Yi Li, Yujun Zhang, Shujie Tan, Jun Han, Xingxing zhang, Zhang Zhang, Xu Cheng, Jun Han, Zhiyi Yu, “Design and Analysis of Highly Energy/area-efficient Multi-ported Register Files with Read Word-line Sharing Strategy in 65nm CMOS Process”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 7, pp. 1365-1369, July 2015.
  6. Jun Han, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, Xiaoyang Zeng, “A Heterogeneous Multicore Crypto-Processor with Flexible Long-Word-Length Computation”, IEEE Transactions on Circuits and Systems I, Vol. 62, No. 5, pp. 1372-1381, May 2015.
  7. Masoud Daneshtalab, Farhad Mehdipour, Zhiyi Yu, Hannu Tenhunen, “Special Issue on emerging Many-core Systems for exascale computing”, ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 11, No. 4, pp. 39, April 2015.
  8. Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng, “A 65 nm Cryptographic Processor for High Speed Pairing Computation”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 4, pp. 692-701, April 2015.
  9. Renfeng Dou, Jun Han, Yifan bo, Zhiyi Yu, Xiaoyang Zeng, “An Efficient Implementation of Montgomery Multiplication on Multicore Platform with Optimized Algorithm, Task Partitioning, and Network Architecture”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 11, pp. 2245-2255, November 2014.
  10. Zheng Yu, Zhiyi Yu, Xueqiu Yu, Ningxi Liu, Xiaoyang Zeng, “Low Power Multicore Processor Design with Reconfigurable Same Instruction Multiple Process”, IEEE Transactions on Circuits and Systems II, VOL. 61, NO. 6, June 2014.
  11. Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming’e Jing, Xiaoyang Zeng, “A 16-core Processor with Shared-Memory and Message-Passing Communications”, IEEE Transactions on Circuits and Systems I, Vol. 61, No. 4, pp. 1081-1094, April 2014.
  12. Jun Han, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng, “Parallelization of Radix-2 Montgomery Multiplication on multicore platform”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 21, No. 12, pp. 2325-2330, December 2013.
  13. Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming'e Jing, Xiaoyang Zeng, Zhiyi Yu, “A 65nm 39GOPS/W 24-Core Processor with 11Tb/s/W Packet Controlled Circuit-Switched Double-Layer Network-on-Chip and Heterogeneous Execution Array”, in IEEE International Solid-State Circuits Conference (ISSCC), February 2013, pp. 56-57.
  14. Zhiyi Yu, Kaidi You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, Haofan Yang, Ming'e Jing, Xiaoyang Zeng, “An 800MHz 320mW 16-Core Processor With Message-Passing and Shared-Memory Inter-Core Communication Mechanisms”, in IEEE International Solid-State Circuits Conference (ISSCC), February 2012, pp. 64-65.
  15. Zhiyi Yu, Bevan Baas, “A Low-Area Multi-link Interconnect Architecture for GALS Chip Multiprocessor”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 18. No. 5, pp.750-762, May 2010.
  16. D. Truong, W. Cheng, T. Mohsenin, Zhiyi Yu, T. Jacobson, G. Landge, M. Meeuwsen, C. Watnik, A. Tran, Z. Xiao, E. Work, J. Webb, P. Mejia, B. Baas, “A 167-processor Computational Platform in 65 nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 44, No. 4, pp. 1130-1144, April 2009.
  17. Zhiyi Yu, Bevan Baas, “High Performance, Energy Efficiency, and Scalability with GALS Chip Multiprocessors”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 17, Issue 1, pp. 66-79, Jan. 2009.
  18. D. Truong, W. Cheng, T. Mohsenin, Zhiyi Yu, T. Jacobson, G. Landge, M. Meeuwsen, C. Watnik, P. Mejia, A. Tran, J. Webb, E. Work, Z. Xiao, B. Baas, “A 167-processor 65 nm Computational Platform with Per-Processor  Dynamic Supply Voltage and Dynamic Clock Frequency Scaling”, in IEEE Symposium on VLSI Circuits, June 2008, pp. 22-23.
  19. Zhiyi Yu, M. Meeuwsen, R. Apperson, O. Sattari, M. Lai, J. Webb, E. Work, D. Truong, T. Mohsenin, B. Baas, “AsAP: An Asynchronous Array of Simple Processors”, IEEE Journal of Solid-State Circuits (JSSC), Vol. 43, No. 3, pp. 695-705, March 2008.
  20. R. Apperson, Zhiyi Yu, M. Meeuwsen, T. Mohsenin, B. Baas, “A Scalable Dual-Clock FIFO for Data Transfers between Arbitrary and Haltable Clock Domains”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 15, No. 10, pp. 1125-1134, October 2007.
  21. B. Baas, Zhiyi Yu, M. Meeuwsen, O. Sattari, R. Apperson, E. Work, J. Webb, M. Lai, T. Mohsenin, D. Truong, J. Cheung, “AsAP: A Fine-grained Many-core Platform for DSP Applications”, IEEE Micro, Vol. 27, No. 2, pp:34-45, March-April 2007.
  22. Zhiyi Yu, M. Meeuwsen, R. Apperson, O. Sattari, M. Lai, J. Webb, E. Work, T. Mohsenin, M. Singh, B. Baas, “An Asynchronous Array of Simple Processors for DSP Applications”, in IEEE International Solid-State Circuits Conference (ISSCC), February 2006, pp:428-429.

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