郭建平

副教授

联系方式:

Emailguojp3@mail.sysu.edu.cn

电话:020-84114462

手机:15202061502

教育经历: 

个人简介:

本科及硕士就读于西安电子科技大学,2011年于香港中文大学获电子工程专业博士学位,目前为中山大学“百人计划”副教授、硕士生导师、IEEE高级会员。主要从事模拟IC的研究与设计,研究方向主要为电源管理IC、无线能量传输与能量采集电路、以及无线通信芯片等。2012年加入中山大学后,依托中山大学ASIC研究中心及国家集成电路人才培养基地,组建模拟及数模混合IC研究小组,目前小组成员包括博士生1名、硕士生5名、本科生5名。

在IC设计领域已发表40多篇国际期刊/会议论文,SCI检索18篇(第一/通讯作者10篇),其中9篇为IEEE期刊论文(3 JSSC,3 TPEL,1 TCAS-I,1 TCAS-II,1 TVLSI)。申请中国发明专利16项(第一发明人11项),一项已获授权。

授课课程: 

模拟电子线路及实验(本科大二)

模拟集成电路设计(本科大三)

模拟集成电路版图设计实验(本科大三)

高级模拟集成电路设计(研究生)

研究方向: 

微电子学与固体电子学/集成电路工程(硕士生导师)

Analog IC Design; Power-Management IC Design

 

科研项目: 

2016−2019,便携式北斗多模导航SoC中的高效率、高集成、高性能电源管理集成电路,广州市珠江科技新星专项,项目负责人

2015−2018,民用高性能低成本北斗导航SoC芯片若干关键技术研究,广东省自然科学基金面上项目,项目负责人

2013−2015,低功耗高性能能量自激型电源管理集成电路,国家自然科学基金青年基金,项目负责人

2012−2013,中山大学“百人计划”引进人才科研启动经费,项目负责人

2014−2015,北斗多模卫星导航芯片关键电路IP核的研究与设计,广东顺德中山大学-卡内基梅隆大学国际联合研究院先导项目,项目协调人(项目负责人:陈弟虎教授)

2012−2014,北斗/GPS多模卫星导航高性能芯片开发及产业化,广东省战略新兴产业关键技术产业化专项,与广州润芯合作申请,中大第一参与人(中大负责人:陈弟虎教授)

代表性科研成果: 
  1. Y. Zheng, M. Ho, J. Guo*(通讯作者), and K. N. Leung, “A Single-Inductor Multiple-Output Auto-Buck-Boost DC-DC Converter with Tail-Current Control,” IEEE Transactions on Power Electronics (TPEL), Vol. 31, No. 11, pp. 7857−7875, Nov. 2016. (SCI, IF: 6.008)
  2. M. Ho, J. Guo, K. H. Mak, W. L. Goh, S. Bu, Y. Zheng, X. Tang, and K. N. Leung*, “A CMOS Low-Dropout Regulator with Dominant-Pole Substitution,” IEEE Transactions on Power Electronics (TPEL), Vol. 31, No. 9, pp. 6362−6371, Sep. 2016. (SCI, IF: 6.008)
  3. M. Ho, J. Guo, T. W. Mui, K. H. Mak, W. L. Goh, H. C. Poon, S. Bu, M. W. Lau, and K. N. Leung*, “A Two-Stage Large-Capacitive-Load Amplifier with Multiple Cross-Coupled Small-Gain Stages,” IEEE Transactions on VLSI Systems (TVLSI), Vol. 24, No. 7, pp. 2580−2592, Jul. 2016. (SCI, IF: 1.245)
  4. K. Sun, L. Chen, J. Guo, D. Teng, and L. Liu, “A LTPS-TFT pixel circuit for active matrix organic light emitting diode based on improved current mirror,” Displays, Vol. 44, No. 9, pp. 1–4, Sep. 2016. (SCI, IF: 1.033)
  5. Y. Zheng, M. Ho, J. Guo, K-L Mak, and K. N. Leung*, “A Single-Inductor Multiple-Output Auto-Buck-Boost DC-DC Converter with Auto Phase Allocation,” IEEE Transactions on Power Electronics (TPEL), Vol. 31, No. 3, pp. 2296−2313, Mar. 2016. (SCI, IF: 6.008, Top accessed TPEL paper in Nov. 2015)
  6. J. Guo*, M. Ho, K. N. Leung, and G. Li, “Digitally-assisted constant-on-time dynamic-biasing technique for bandwidth and slew-rate enhancement in ultra-low-power low-dropout regulator,” International Journal of Circuit Theory and Applications (IJCTA), Vol. 44, No. 2, pp. 504−513, Feb. 2016. DOI: 10.1002/cta.2091. (SCI, IF: 1.254)
  7. K. H. Mak, M. W. Lau, J. Guo, T. W. Mui, M. Ho, W. L. Goh, and K. N. Leung*, “A 0.7-V 24-µA Hybrid OTA Driving 15-nF Capacitive Load with 1.46-MHz GBW,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 50, No. 11, pp. 2750−2757, Nov. 2015. (SCI, IF: 3.009, Top 1 journal in IC design, Top accessed JSSC paper in Oct. and Nov. 2015)
  8. M. Huang, D. Chen, J. Guo*, H. Ye, K. Xu, X. Liang, and Y. Lu, “A CMOS Delta Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), Vol. 62, No. 7, pp. 1716−1725, Jul. 2015. (SCI, IF: 2.403)
  9. M. Huang, D. Chen, Z. Wang, J. Guo*, E. H. Dagher, B. Xu, K. Xu, H. Ye, W. Zheng, Z. Liang, X. Liang, and W. K. Masenten, “A power-area-efficient, 3-band, 2-RX MIMO, TD-LTE receiver with direct-coupled ADC,” International Journal of Circuit Theory and Applications (IJCTA), pp. 806−821, Jun. 2015. (SCI, IF: 1.254)
  10. J. Guo*, M. Ho, K. Y. Kwong, and K. N. Leung, “Power-Area-Efficient Transient-Improved Capacitor-Free FVF-LDO With Digital Detecting Technique,” IET Electronics Letters (EL), Vol. 51, No. 1, pp. 94–96, Jan. 2015. (SCI, IF: 0.930, Top accessed EL paper in Jan., Mar., Apr., and Jun., 2015)
  11. M. Huang, D. Chen, J. Guo*, K. Xu, H. Ye, X. Liang, E. H. Dagher, B. Xu, and W. K. Masenten, “A Tri-Band, 2-RX MIMO, 1-TX TD-LTE CMOS Transceiver,” Microelectronics Journal, Vol. 46, No. 1, pp. 59−66, Jan. 2015. (SCI, IF: 0.836)
  12. T. W. Mui, M. Ho, K. H. Mak, J. Guo, H. Chen, and K. N. Leung*, “An Area-Efficient 96.5%-Peak-Efficiency Cross-Coupled Voltage Doubler With Minimum Supply of 0.8V,” IEEE Transactions on Circuits and Systems II: Express Brief (TCAS-II), Vol. 61, No. 9, pp. 656−660, Sep. 2014. (SCI, IF: 1.234)
  13. J. Guo and K. N. Leung*, “A CMOS Voltage Regulator for Passive RFID Tag ICs,” International Journal of Circuit Theory and Applications (IJCTA), Vol. 40, No. 4, pp. 329−340, Apr. 2012. (SCI, IF: 1.254)
  14. J. Guo and K. N. Leung*, “A 6-µW Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 45, No. 9, pp. 1896−1905, Sep. 2010. (SCI, IF: 3.009; Top 1 journal in IC design; Most accessed JSSC paper in Sep. 2010, ranked 7th and 10th of the top 10 accessed JSSC paper in Oct. 2010 and Nov. 2010, respectively; Ranked 14th and 100th of the top 100 downloaded documents in Sep. 2010 and Nov. 2010, respectively, in IEEE Xplore)
  15. C. F. Chan, K. P. Pun*, K. N. Leung, J. Guo, L. L. K. Leung, and C. S. Choy, “Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 45, No. 3, pp. 587−599, Mar. 2010. (SCI, IF: 3.009; Top 1 journal in IC design)
  16. J. Guo*, Y. Cao, and X. Lai, “An Inner ESR-Fungible Compensation Technique for CMOS Low Dropout Regulator,” Analog Integrated Circuits and Signal Processing (AICSP), Vol. 61, No. 3, pp. 265−270, Dec. 2009. (SCI, IF: 0.468)
  17. X. Lai, J. Guo*, Z. Sun, and J. Xie, “A 3-A CMOS Low Dropout Regulator with Adaptive Miller Compensation,” Analog Integrated Circuits and Signal Processing (AICSP), Vol. 49, No. 1, pp. 5−10, Oct. 2006. (SCI, IF: 0.468)
  18. J. Guo and K. N. Leung, “A 25mA CMOS LDO with −85dB PSRR at 2.5MHz,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore, pp. 381−384, Nov. 2013.
  19. J. Guo and K. N. Leung, “High PSRR LDO with Embedded Ripple Feed-Forward Path,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, California, USA, Student Research Preview, Feb. 20, 2011. (Top 1 conference in IC design, also known as "the Chip Olympics",Student Travel Grant Award).

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